1. Field of the Invention
The present invention relates generally to chemical mechanical polishing and planarization of semiconductor devices. More specifically, the invention relates to a method and composition for removing a barrier layer in chemical mechanical polishing.
2. Background of the Related Art
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity for conductors and to use materials having a low dielectric constant (low k, defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.
One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current carrying capacity, and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch. Achieving precise pattern etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing semiconductors with copper interconnects are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical and horizontal interconnects. Conductive materials (such as copper) and other materials (such as barrier layer materials used to prevent diffusion of conductive material into the surrounding low k dielectric) are then inlaid into the etched pattern. Barrier layer materials include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN). Conductive material and barrier layer material external to the interconnects, such as on the field of the substrate is removed.
One method of removing the excess deposited conductive material and barrier layer material is through planarizing or “polishing” the surface of the substrate. Planarization is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is also used to form an even surface for subsequent levels of metallization or processing as a substrate may become non-planar due to prior layers of materials which were previously deposited and removed. Planarization is also useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition to effect both chemical activity and mechanical activity. Typically, the polishing composition is in the form of a slurry containing a polishing agent, such as finely-dimensioned alumina (Al2O3), silica (SiO2), titania (TiO2), or ceria (CeO2) particles. Typically, the polishing composition additionally contains a number of chemicals, depending upon the materials to be polished, including pH adjusting and stabilizing agents, as well as chemical oxidizing agents for chemically reacting with various components of the surface being polished/planarized.
Conventionally, in polishing copper features, such as dual damascenes, the copper material is polished to the barrier layer, and then the barrier layer is polished to the underlying dielectric layer to form the dual damascene feature. One challenge which is present in polishing of copper material and barrier layer material is that it is difficult to polish residual conductive material remaining at the interface between the conductive material layer and the barrier layer. Therefore, overpolishing of the conductive material at the interface is necessary to ensure all of the conductive material is removed prior to subsequent barrier layer removal. However, overpolishing of the conductive material at the interface can result in dishing or erosion of the conductive material layer in the features.
FIG. 1 is a schematic view of a substrate illustrating the phenomenon of dishing. Conductive lines 211 and 212 are formed by depositing conductive material, such as copper or copper alloy, in a feature definition formed in the dielectric layer 210, typically comprised of silicon oxides or other dielectric materials. After planarization, a portion of the conductive material is depressed by an amount D, referred to as the amount of dishing, forming a concave copper surface. Dishing results in a non-planar surface that impairs the ability to print high resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.
Another difficulty encountered is that current slurries used for barrier layer removal typically include a large concentration of abrasives and harsh chemical such as oxidizing agents. Furthermore, a high down force is applied to the substrate against the polishing pad to effect polishing of the barrier layer. As a consequence, the removal rate of the barrier layer is hard to control. Therefore polishing and/or overpolishing of the barrier layer may also result in dishing and erosion of the conductive material layer in the features and may result in dishing erosion of the dielectric layer. Still, the removal rate of the barrier layer for these slurries is very low resulting in a low throughput.
Therefore, there exists a need for a method and related CMP composition which facilitates the removal of a conductive material layer and a barrier layer, and provides selectivity therebetween and to an underlying dielectric layer.